As feature sizes of metal-oxide-semiconductor (MOS) and complementary metal-oxide-semiconductor (CMOS) devices are reduced into the deep sub-micron range, so-called “short-channel” effects arise which tend to limit device performance. Deep junctions, as provided in PMOS devices, and high-on resistance, are problematic for voltages less than 2V.
For P-channel MOS transistors of short-channel type, the major limitation on performance arises from “punch-through” effects which occur with relatively deep junctions. In such instances, there is a wider sub-surface depletion effect and it is easier for the field lines to extend from the drain region to the source region, resulting in the above-mentioned “punch-through” current problems and device shorting. To minimize this effect, relatively shallow junctions are employed in forming P-channel MOS transistors. The most satisfactory solution to date of hot carrier instability problems of MOS devices is the provision of shallow source/drain extensions driven just under the gate electrode region, while the heavily-doped drain region is laterally displaced away from the gate by use of a sidewall spacer on side surfaces of the gate electrode. Such structures are particularly advantageous in avoiding large lateral diffusion, and the channel length can be set precisely.
In order to reduce contact resistance and increase device speed, metal silicide layers are conventionally formed on source/drain regions. As device geometries continue to plunge into deep sub-micron range, the need to accurately control the thickness of sidewall spacers formed on side surfaces of gate electrodes becomes increasingly significant. For example, a gate electrode may be formed over a semiconductor substrate with a gate dielectric layer therebetween and the sidewall spacers on side surfaces thereof. The sidewall spacers can comprise silicon oxide, a silicon nitride or a silicon oxynitride, for example. Shallow source/drain extensions are typically formed using the gate electrode as a mask prior to forming these sidewall spacers.
Subsequently, ion implantation is typically conducted using the gate electrode and sidewall spacers as a mask to form moderately- or heavily-doped and deeper source/drain regions. The thickness of the sidewall spacers is significant in at least two respects. Initially, the thickness of the sidewall spacer controls the length of the shallow source/drain extension. In addition, the width of the sidewall spacers controls the distance between the metal silicide layers and the side surfaces of the gate electrode.
Silicide, such as nickel silicide, can encroach on the polysilicon gate electrode by lateral diffusion underneath the sidewall spacers. If the encroachment is large enough, the device is rendered unusable. It is therefore desirable to detect encroachment of the silicide on the polysilicon gate electrode. Detection of the potential encroachment is difficult by electrical testing. One problem with electrical testing is that the wafer has to be processed to metal 1 (M1) before the electrical testing can be performed. This is wasteful of processing steps if the silicide encroachment has already rendered the part unusable. Furthermore, since the silicide encroachment occurs underneath the spacer material, the encroachment cannot be detected by optical or electron microscope analysis. These limitations have previously rendered silicide encroachment practically undetectable.